In a semiconductor memory device having high-density and large-capacitance, as a cell area physically occupied by each memory cell becomes smaller, the width of a word line and a bit line becomes narrower and a layout of a sense amplifier becomes more delicate and precise. In fact, in a DRAM device of a mega scale (2.sup.20), an extremely strict design rule of a sub-micron unit is required, as is well known in this field. Therefore, to manufacture such DRAM device with this strict design rule, it is essential to achieve the optimal arrangement of the semiconductor memory devices within a limited space.
FIG. 1 illustrates the construction of a known semiconductor memory device. Such known semiconductor memory device 10 is divided into four blocks. Referring to each block, a memory cell array 20 including a sense amplifier is surrounded by a column decoder 30 and a row decoder 60. A word line driver stage 50 is interposed between the memory cell array 20 and the row decoder 60. The word line driver stage 50 selects a relevant word line in response to decoding signals from the row decoder 60 in order to enable access to selected memory cells of the memory cell array 20. The remaining area of the semiconductor memory device 10 excluding the memory cell array 20, the column decoder 30, the row decoder 60 and the word line driver stage 50, represents a peripheral region 11 thereof
The connection between the word line driver stage 50 and the memory cell array 20, concerning the conventional memory device of FIG. 1, can be easily understood by referring to a U.S. Pat. No. 4,481,609.
FIG. 2, referred to from the above referenced patent, illustrates a part of FIG. 1 in more detail. Within each memory cell array, a plurality of word lines WL and a plurality of bit lines BL cross one another at right angle (in FIG. 2, a 10.times.10 arrangement is shown as an example), and memory cells 21 are arranged at the intersections between the word lines and bit lines. Through a column select circuit 31(called Y gate) gated by a decoding signal of the column decoder 30, the bit lines BL are selected. The column select circuit 31 is connected to the sense amplifier 22. All the word lines WL1-WL10 in the memory cell array 20 are connected to the word line driver stage 50, that is, the word line driver stage 50 has a number of word line drivers as many as the number of the word lines, as shown in FIG. 3A.
Referring to FIG. 3A illustrating the above strapping in a more easily understandable form, the word line driver stage 50 has the same number of the word line drivers as that of the word lines in the memory cell array 20. However, the employment of such constitution of the memory cell in a high density memory cell device requires a lengthy word line, and thereby, increasing the line resistance of each word line and delaying the signal transmissions. In an attempt to overcome this disadvantage, i.e., the delay of the signal transmissions, the word line is strapped with a metal line.
FIG. 3B shows that the word line WL and the metal line ML are strapped together. As for a metal strapped-region 52 formed by the conventional method, the greater the number of the metal strapped regions is, the greater the area on the semiconductor memory device physically occupied by these metal strapped regions is. This fact imposes an adverse affect on the design rule and the layout task. Therefore, the conventional strapping method of the word line and the metal line has unsurmountable limit.
Meanwhile, there is another conventional construction providing a more effective arrangement of the word line drivers which drive the word lines suitable for the high density semiconductor device. In this construction, the word line driver stages are disposed at the opposite edges of the memory cell array 20 as shown in FIG. 1, thus each word line driver has two word line pitches. Accordingly the layout problem required by the fine design is overcome. Like the construction disclosed in FIG. 1, however since each word line from each word line driver is extended to the end of the memory cell array, the line resistance and the parasitic capacitance in the word line itself are increased, and the delay of the signal transmissions is provided.